Slow and Steady: Measuring and Tuning Multicore Interference Demo
Dan Iorga (Imperial College)

Iorga.pdf Poster Talk Slides
Demo  Video
Slack Thread

Now ubiquitous, multicore processors provide replicated compute cores that allow independent programs to run in parallel. However, shared resources, such as last-level caches, can cause otherwise-independent programs to interfere with one another, leading to significant and unpredictable effects on their execution time. Indeed, prior work has shown that specially crafted enemy programs can cause software systems of interest to experience orders-of-magnitude slowdowns when both are run in parallel on a multicore processor. This undermines the suitability of these processors for tasks that have real-time constraints.

In this work, we explore the design and evaluation of techniques for empirically testing interference using enemy programs, with an eye towards portability (how interference testing can be effective across chips). The reliability of our measurements allows us to explore auto-tuning, where enemy programs are further specialised per architecture. We evaluate the slowdowns caused by our approach on a simple vector addition program. We envision that empirical approaches, such as ours, will be valuable for `first pass’ evaluations when investigating which multicore processors are suitable for real-time tasks.

Bucket of Ignorance: A Hybrid Data Structure for Timing Mechanism in Real-Time
Marcel Ebbrecht (TU Dortmund)
Kuan-Hsun Chen (TU Dortmund)
Jian-Jia Chen (TU Dortmund)

Ebbrecht_CC.pdf Poster Talk Slides
Slack thread

To maintain deterministic timing behaviors, Real-Time Operating Systems (RTOSes) require not only a task scheduler but also a timing mechanism for the periodicity of recurrent tasks. Most of existing open-source RTOSes implement either a tree-based or a list-based mechanism to track which task is ready to release on-the-fly. Although tree-based mechanisms are known to be efficient in time complexity for searching operations, the additional effort processing removals and insertions are also not negligible, which may countervail the advantage, compared to list-based timer-managers, even with small task sets. In this work, we provide a simulation framework, which is ready to be released, to investigate existing timing mechanisms and analyze how do they perform under certain conditions. Throughout extensive simulations, we show that our proposed solution indeed requires less computation effort than conventional timing mechanisms when the size of task set is in the range of 16 to 208.

Measurement-Based Estimation of the Worst-Case Execution Time of Consecutive Jobs
Rômulo Silva de Oliveira (Universidade Federal de Santa Catarina
Luís Almeida (Universidade do Porto)

Oliveira_A.pdf Poster Talk Slides
Slack Thread

WIP: The classic task model used for real-time scheduling analysis includes a single parameter C that represents the worst-case execution time of a task, and it can occur at every single job of that task. Many works in the past extended this model, providing a richer description of a task in terms of the execution time of several consecutive jobs. But when one considers the collective execution time of consecutive jobs, it is necessary to take into account aspects such as the hardware state and the application state between jobs and also input data patterns from the environment. Such complexity precludes the use of static analysis. In this paper we consider the use of measurement-based probabilistic timing analysis to obtain estimates for the worst-case execution time of a task, considering several consecutive jobs. We define function Gamma Factor to describe by how much the interference a task generates is reduced when sequences of jobs are explicitly considered. A set of experiments is used to investigate the applicability and potential gain of this method.

MCsim: An Extensible Memory Controller Simulation Framework
Reza Mirosanlou (University of Waterloo)
Danlu Guo (University of Waterloo)
Mohamed Hassan (McMaster University)
Rodolfo Pellizzoni (University of Waterloo)

Mirosanlou_GHP.pdf Poster Talk Slides
Video Demo
Slack Thread

Recently, many proposals for designing memory controllers have been exposed. Interest has since been growing in the area of computer architecture and real-time systems. Such controllers mainly improve the throughput of the system and/or guarantee timing requirements through unique scheduling algorithms. Consequently, a demand for a comprehensive simulation framework is sensed in order to provide an infrastructure for the development of new ideas effectively without re-implementing the other parts of the hardware. In this article, we demonstrate MCsim, a cycle-accurate, extensible, DRAM memory controller simulator.