Note: these are not in any particular order, and titles may change before final publication.

Paper TitleAuthorAffiliation
Scheduling Computational and Energy Harvesting Tasks in Deadline-Aware Intermittent SystemsBashima IslamUniversity of North Carolina at Chapel Hill
Shahriar NirjonUniversity of North Carolina at Chapel Hill
Real-Time Scheduling upon a Host-Centric Acceleration Architecture with Data OffloadingJinghao SunNortheastern University
Jing LiNew Jersey Institute of Technology
Zhishan GuoUniversity of Central Florida
An ZouWashington University in St. Louis
Xuan ZhangWashington University in St. Louis
Kunal AgrawalWashington University in St. Louis
Sanjoy BaruahWashington University in St. Louis
On Dynamic Thermal Conditions in Mixed-Criticality SystemsSeyedmehdi HosseinimotlaghUniversity of California, Riverside
Ali GhahramannezhadUniversity of California, Riverside
Hyoseung KimUniversity of California, Riverside
Debugging FPGA-accelerated Real-time SystemsMartin GeierTechnical University of Munich
Marian BrändleTechnical University of Munich
Dominik FallerTechnical University of Munich
Samarjit ChakrabortyTechnical University of Munich
Enforcing Deadlines for Skeleton-based Parallel ProgrammingPaul MetzgerUniversity of Edinburgh
Murray ColeUniversity of Edinburgh
Christian FenschUniversity of Edinburgh
Marco AldinucciUniversity of Turin
Enrico BiniUniversity of Turin
A novel flow control mechanism to avoid multi-point progressive blocking in hard real-time priority-preemptive NoCsLeandro IndrusiakUniversity of York
Alan BurnsUniversity of York
Nickolay SmirnovUniversity of York
James HarrisonUniversity of York
Boomerang: Real-Time I/O Meets Legacy SystemsRichard WestBoston University
Ahmad GolchinBoston University
Soham SinhaBoston University
Time-Triggered Traffic Planning for Data Networks with Conflict GraphsJonathan FalkUniversity of Stuttgart
Frank DürrUniversity of Stuttgart
Kurt RothermelUniversity of Stuttgart
Co-Optimizing Performance and Memory Footprint Via Integrated CPU/GPU Memory Management, an Implementation on Autonomous Driving PlatformSoroush BateniUniversity of Texas at Dallas
Zhendong WangUniversity of Texas at Dallas
Yuankun ZhuUniversity of Texas at Dallas
Yang HuUniversity of Texas at Dallas
Cong LiuUniversity of Texas at Dallas
Slite: OS Support for Near Zero-Cost, Configurable SchedulingPhani Kishore GadepalliThe George Washington University
Runyu PanThe George Washington University
Gabriel ParmerThe George Washington University
Interference-Aware Memory Allocation for Real-Time Multi-Core SystemsSimon RederKarlsruhe Institute of Technology (KIT)
Juergen BeckerKarlsruhe Institute of Technology (KIT)
Timing of Autonomous Driving Software: Problem Analysis and Prospects for Future SolutionsMiguel AlconBarcelona Supercomputing Center (BSC)
Hamid TabaniBarcelona Supercomputing Center (BSC)
Leonidas KosmidisBarcelona Supercomputing Center (BSC)
Enrico MezzettiBarcelona Supercomputing Center (BSC)
Jaume AbellaBarcelona Supercomputing Center (BSC)
Francisco J. CazorlaBarcelona Supercomputing Center (BSC)
Real-Time Replica Consistency over Ethernet with Reliability BoundsArpan GujaratiMPI-SWS, Germany
Sergey BozkhoMPI-SWS, Germany
Björn B. BrandenburgMPI-SWS, Germany
Addressing Resource Contention and Timing Predictability for Multi-Core Architectures with Shared Memory InterconnectsHaitong WangU of York
Neil AudsleyU of York
Wanli ChangU of York
Bringing Inter-Thread Cache Benefits to Federated SchedulingCorey TesslerWayne State University
Prashant ModekurthyWayne State University
Nathan FisherWayne State University
Abusayeed SaifullahWayne State University
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned SchedulingDaniel CasiniScuola Superiore Sant’Anna
Alessandro BiondiScuola Superiore Sant’Anna
Geoffrey NelissenCISTER, ISEP, Polytechnic Institute of Porto
Giorgio ButtazzoScuola Superiore Sant’Anna
CARSS: Client-Aware Resource Sharing and Scheduling for Heterogeneous ApplicationsILJOO BaekCarnegie Mellon University
Matthew HardingCarnegie Mellon University
Akshit KandaCarnegie Mellon University
Kyung Ryeol ChoiGeorge Washington University
Soheil SamiiGM Motor R&D
Ragunathan (Raj) RajkumarCarnegie Mellon University
Cache-aware response time analysis for real-time tasks with fixed preemption pointsFilip MarkovicMalardalen University
Jan CarlsonMalardalen University
Radu DobrinMalardalen University
Slow and Steady: Measuring and Tuning Multicore InterferenceDan IorgaImperial College London
Tyler SorensenPrinceton University
John WickersonImperial College London
Alastair DonaldsonImperial College London
BRU: Bandwidth Regulation Unit for Real-Time Multicore ProcessorsFarzad FarshchiUniversity of Kansas
Qijing HuangUniversity of California, Berkeley
Heechul YunUniversity of Kansas
Sharing-aware Data Acquisition Scheduling for Multiple Rules in the IoTSeonyeong HeoPOSTECH
Seungbin SongYonsei University
Bongjun KimPOSTECH
Hanjun KimYonsei University
SubFlow: A Dynamic Induced-Subgraph Strategy Toward Real-Time DNN Inference and TrainingSeulki LeeUniversity of North Carolina at Chapel Hill
Shahriar NirjonUniversity of North Carolina at Chapel Hill
Bounded-time recovery for distributed real-time systemsNeeraj GandhiUniversity of Pennsylvania
Edo RothUniversity of Pennsylvania
Robert GiffordUniversity of Pennsylvania
Linh Thi Xuan PhanUniversity of Pennsylvania
Andreas HaeberlenUniversity of Pennsylvania
DRAMbulism: Balancing Performance and Predictability through Dynamic PipeliningReza MirosanlouUniversity of Waterloo
Mohamed HassanMcMaster University
Rodolfo PellizzoniUniversity of Waterloo
Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP)Jeremy GiesenBarcelona Supercomputing Center (BSC)
Pedro BenedicteBarcelona Supercomputing Center (BSC)
Enrico MezzettiBarcelona Supercomputing Center (BSC)
Jaume AbellaBarcelona Supercomputing Center (BSC)
Francisco J. CazorlaBarcelona Supercomputing Center (BSC)
The Potential of Programmable Logic in the Middle: Cache BleachingShahin RoozkhoshBoston University
Renato MancusoBoston University
Real-Time Object Detection System with Multi-Path Neural NetworksSeonyeong HeoPOSTECH
Sungjun ChoPOSTECH
Youngsok KimYonsei University
Hanjun KimYonsei University
Dissecting the CUDA scheduling hierarchy: a Performance and Predictability PerspectiveIgnacio SañudoUniversity of Modena and Reggio Emilia
Nicola CapodieciUniversity of Modena and Reggio Emilia
Jorge Luis Martinez GarciaUniversity of Modena and Reggio Emilia
Andrea MarongiuUniversity of Modena and Reggio Emilia
Marko BertognaUniversity of Modena and Reggio Emilia
Latency-Aware Generation of Single-Rate DAGs from Multi-Rate Task SetsMicaela VerucchiUniversity of Modena and Reggio Emilia, Technical University of Munich
Mirco TheileTechnical University of Munich
Marco CaccamoTechnical University of Munich
Marko BertognaUniversity of Modena and Reggio Emilia